1. Field of the Invention
This invention relates to digital memory systems, and more particularly to parity generation and error detection for memory subsystems.
2. Description of the Related Art
Computers using memory such as Dynamic Random-Access Memory (DRAM) are well know in the art. Because of the very large size of such memories, even a very small error rate could cause serious operating failures. Error detection and even error correction methods have been employed to detect errors in DRAM memory and subsystems.
Personal computers, such as the IBM AT and compatibles, have included error detection in the form of parity. Parity is simply the "pairing" off of the data bits. If an even number of "1" bits is counted parity is true, while if an odd number of "1"s is counted parity is false. This is known as "Even" parity--an even number of "1"s produces a true or "1" output. A second type, "Odd" Parity, is true if an odd number of "1"s is counted. Since the two types of parity are mutually exclusive, an even parity generator will always output the opposite, or inverse logic value, that an odd parity generator would output when the same data word is input.
When 8 bits of data are written to the DRAM, parity is generated for the 8 bits and stored as a 9th bit in the DRAM array. Thus the DRAM is arranged as 9-bit data words; 8 bits of data and a 9th bit for storing the parity. Upon reading from the DRAM, the 8 data bits are input into a parity checker, which computes the parity and then compares it to the parity bit which was previously stored in the 9th bit location in the DRAM array.
When the parity checker finds that the parity bit does not match the previously stored parity bit, a parity error is detected. In the IBM AT computer, an interrupt is signaled and the computer halts operation. This prevents the error from being propagated, which could damage important system files.
Other small computer systems, such as those manufactured by Apple Computer, do not include error detection at all. Thus memory is organized in 8-bit words, which is less expensive than 9-bit words.
A second development in the Personal Computer industry has been the widespread acceptance of Single In-Line Memory Modules (SIMMs), such as is described in U.S. Pat. No. 4,656,605, issued Feb. 23, 1988 to James E. Clayton, hereby incorporated by reference. Clayton shows 8 memory chips mounted on a small epoxy-glass module board or substrate with a 9th memory chip also mounted for storing parity information. Other SIMMs with only 8 memory chips are also available, but these do not support parity checking. In addition, the terminal configuration and physical connectivity are different for 8-bit and 9-bit SIMMs, thus making the two incompatible.
A very large number of AT-compatible computers are now being built that accept 9-bit SIMMs. The high volume of SIMMs being manufactured has lowered the cost of memory, and higher-density memory subsystems can be designed using SIMMs, since the SIMMs are relatively small modules, having a length and width just adequate to mount the 8 or 9 DRAM chips possibly a few capacitors to suppress voltage transients or spikes, and the interconnection needed. These SIMMs are usually mounted at an angle to the mother board, allowing several SIMMs to be mounted in a small area of the mother board since the SIMM modules themselves stick up, out of the plane of the mother board. Often additional slots are included on the system mother board so the user can add additional SIMMs subsequent to manufacture and purchase of the PC.
A third development has been the increasing reliability of the DRAM chips themselves. DRAM errors are much less common than when the PC was first introduced. In fact, errors are so infrequent now that the need for error detection is questionable. At the same time, costs of Personal Computers have dropped dramatically, and profit margins have been squeezed by intense competition, making it desirable to eliminate the cost of the 9th data bit, especially since the value of parity checking is questionable.
However, simply using 8-bit-wide SIMMs is impractical, because of the physical incompatibility. In addition, the PC system may still perform parity checking unless parity checking is disabled, which requires modification of the system software. Modifying the system software, called the BIOS on an IBM AT or compatible, is undesirable because it can be difficult for the end user to change, usually requiring replacement of a ROM chip.
Some newer CPU chips have 9-bit data busses rather than the standard 8-bit busses. These CPUs perform parity checking themselves, rather than the memory controller subsystem on the mother board. This further complicates disabling of the parity checking.
If a system already contains 9-bit memory, and the user wishes to upgrade, using 8-bit memory would typically require disabling parity checking for all memory, including the older, less reliable 9-bit memory. Ideally, parity checking would still be performed on the older 9-bit memory, but not on the newer, more reliable 8-bit memory. In fact, checking for errors on the system board, or mother board, is still desirable, since physical connections such as solder and printed-circuit board traces may fail.
What is desired is an 8-bit SIMM that is physically compatible with 9-bit SIMMs, and yet still allows parity checking to occur on the motherboard and for other 9-bit SIMMs present.